1. Field of the Invention
This invention relates generally to automated test equipment (ATE) using digital test vectors to locate faulty components on circuit boards, and more specifically, to an online method for editing or "patching" compressed test vectors stored in an automated circuit test system, without having to recompile the test vector source code program.
2. Statement of the Problem
As the complexity of digital devices increases, the number of test steps required to test these devices also increases. When tests are performed at a circuit board level, the number of test steps are further increased as advancements in technology allow greater device density on circuit boards. Because of the vast number of steps required to test modern circuit boards, computer-automated testing is necessitated. Before a computer-automated test can be run on a circuit board, however, a source code program for controlling the test must be manually generated. This test program source code must then be compiled into computer-readable object code before the test can be run. As circuit board complexity increases, the time required to compile the source code to test the circuit board increases commensurately. Compile times of hours, and in some cases, days, are not uncommon when compiling test program source code. This lengthy process of compilation presents a significant problem when changes must be made to the test program object code when a program is being debugged or when a test is being run.
Automated circuit test systems typically use a plurality of parallel digital test signals to test circuit boards. The states of these test signals are determined by computer-generated entities called digital test "vectors." A vector is a representation of a set of parallel events to be performed by "drivers" and "receivers." A driver is a device which applies a stimulus to a specific input on a circuit under test. A receiver, or comparator, is a device which allows observation of a specific output from a circuit under test. A digital test vector can be represented as a string of characters, wherein each character may be either a binary digit or a "K" or "T". Each character in the vector represents a signal state to be either applied to or received from the circuit under test. For example, the vector "10" could indicate that a logical "1" is to be applied via a driver to an input test point, while a logical "0" is expected to be detected by a receiver at another test point. The states "K" and "T", for example, are used to indicate that the logical state of a previously applied or detected vector is to be kept or toggled (inverted), respectively.
Each character in a vector corresponds to a specific channel in a test system, with all channels being in parallel, and each channel applying or receiving a single test stimulus at essentially the same time.
In a typical test scenario, a vector is executed, which causes a signal to be applied to the circuit under test, and a subsequent output resulting from the applied signal is received and compared with an expected signal to determine whether the circuit is functioning properly. Since a single vector represents only a single test event, it can be seen that in order to provide diagnostic data, more than one vector must be executed. Typically, many vectors in sequence are required to complete a test, if a reasonable probability of a correct diagnosis is to be achieved.
Each vector used in a given test is stored in test system random access memory ("RAM") on a connector board (called a "pin card") external to a test system computer. It is desirable to have each pin card RAM be of sufficient size to accommodate all vectors required for an entire test. The alternative is to require repeated, time-consuming downloading of vectors to the pin card RAM. Obviously, then, reducing the number of vectors used in a given test accordingly reduces the amount of RAM required in the test system, if all vectors required for an entire test are to be stored in pin card RAM. Many test systems have a multiplicity of pin cards per computer, in order to test more than one circuit board at a time. In such a situation, therefore, the additional number of vectors required for a given test becomes even more of a cost factor.
Vector compression techniques were thus developed to reduce the number of vectors required to perform a given test. At least two forms of vector compression are used in prior art systems such as HEWLETT-PACKARD board tester models 3065 and 3070. The first form of vector compression is called "indirect vector compression" and the second form is called "keep/toggle (K/T) compression." A circuit tester using K/T compression is described in U.S. Pat. Nos. 4,652,814, 4,598,245 and 4,642,561 to Groves, et al. Both forms of vector compression are also discussed below.
A problem with vector compression, however, was that there was no prior art method for the online (or "real time") editing or patching of compressed vectors during test program debug or at circuit board test time. Any modification to the object code test program used by the test system required a lengthy re-compilation of the entire test program source code.
At least two prior art techniques have been developed which allow online modification of uncompressed test vectors (as in the TERADYNE L200/L300 Series), or which allow vector modification with less-than-total recompilation (as with the GENRAD 227x series), but no known prior art technique allows online editing of compressed vectors.
3. Solution to the Problem
The above problems are solved, and an innovation achieved in the field, by the method of the present invention. The present invention provides a method for editing compressed digital test vectors in object code form, without requiring re-compilation of the test program source code. Changes are thus quickly effected, and numerous hours are saved in comparison to systems requiring re-compilation.
In order to test the functional integrity of a digital circuit board, a predetermined set of test vectors, or "test patterns," is applied to the circuit board. This set of test vectors is generated by using a computer to compile manually created source code into a computer-readable sequence of test vectors executable by an automated circuit test system. When executed, the vectors cause corresponding target vector signals to be output to, or indicate the signal expected to be received from, the circuit under test.
Often, however, the source code from which the object code vectors are generated contains one or more incorrect vectors, often called "bugs." A test vector is therefore modified, typically, to correct a "bug" in the compiled test program.
The hardware environment in which the present method functions includes three areas of random access memory (RAM): Program RAM, for storing test commands; sequence RAM, for storing pointers to test vectors, and vector RAM, for storing the test vectors for a given test. Each test command has a pointer to an entry in sequence RAM, which, in turn, has a pointer to a test vector.
The method of the present invention can now be summarized as follows:
(a) First, a new vector n' is created in vector RAM by storing a copy of the target vector n to be modified in vector RAM;
(b) Next, pointers in RAM are adjusted to point to the new vector n'; then
(c) in order to compensate for "K/T" compression, the vector (n+1) following target vector n must be examined to determine whether it requires modification. If vector (n+1) vector requires modification, then a copy (n+1)' of vector (n+1) must first be created in vector RAM. If it is required that vector (n+1)' be created, then vector (n+1) is created and located by repeating steps (a) and (b), above.
(d) Finally, vector n' in vector RAM is modified per user input, and vector (n+1)', if created, is modified to compensate for the effect(s) of K/T compression.
There are two types of commands in program RAM that determine which test vectors are to be applied to the circuit to be tested, and the sequence in which they are applied. The first type of command is a command for applying a single vector to the circuit under test, and is called an APPLY command. The second type of command is a command for applying n vectors pointed to by n sequentially stored entries in sequence RAM, and is called a SEND LINEAR SEQUENCE ("SLS") command.
Using this command terminology, step (b), above, more specifically encompasses:
(1) The command that has vector n as its target is located in program RAM; PA0 (2) if the command located in program RAM is an "SLS" command, then the command is split into a combination consisting of an SLS command and an APPLY command; and PA0 (3) all program contents following the APPLY command are then shifted down by one location, to accommodate the additional instruction resulting from the command being split. A new entry in sequence RAM is created. The new sequence RAM entry is set to point to vector n in vector RAM, and the APPLY command is set to point to the new entry in sequence RAM.
In previous systems using compressed vector formats, a re-compilation of the test source code was necessitated in order to generate a new set of test vectors. The present invention solves this problem by providing for a method of modifying "K/T" format vectors, as well as "indirect" vectors, while obviating the need for recompilation of the test source code. Since the present method works with compressed vectors, the amount of RAM 114 required to store vectors on pin cards is substantially reduced, thereby accordingly reducing the cost of the test system.
Because, in the present invention, modifications to test vectors are made only in object code, these modifications are in effect for only the debug or the test session, and the permanent source code remains unaltered. Any desired changes to the source code can be subsequently made to the test program, and the test program recompiled when sufficient time is available.
Furthermore, all modifications are built upon the existing representation of the test vector object code. Thus, as a test session or debug session is run, subsequent modifications to the test object code are made cumulatively without affecting any modifications previously made to object code. Therefore, no check of vector modification history need be made before making subsequent modifications.